Field of the Invention
Embodiments of the present invention generally relate to pixel rate balancing across multiple processing cores in video coding.
Description of the Related Art
The Joint Collaborative Team on Video Coding (JCT-VC) of ITU-T WP3/16 and ISO/IEC JTC 1/SC 29/WG 11 is currently developing the next-generation video coding standard referred to as High Efficiency Video Coding (HEVC). Similar to previous video coding standards such as H.264/AVC, HEVC is based on a hybrid coding scheme using block-based prediction and transform coding. First, the input signal is split into rectangular blocks that are predicted from the previously decoded data by either motion compensated (inter) prediction or intra-prediction. The resulting prediction error is coded by applying block transforms based on an integer approximation of the discrete cosine transform, which is followed by quantization and entropy coding of the transform coefficients.
To support coding on multi-core computing platforms, some parallel-processing tools are included in HEVC. In addition to the slices introduced in H.264/AVC, these tools include tiling, wavefront parallel processing, and entropy slices. These parallel-processing tools have been defined with the focus mostly on ensuring that if the tools are used in an encoder, a significant burden is not imposed on a single core decoder. However, for ultra high definition (UHD) video coding, multi-core devices are needed in both the encoder and the decoder. It is important that HEVC (and future video coding standards) enables parallel processing capability on the decoder side as well as on the encoder side.